1. Field of the Invention
The present invention generally relates to a jitter detection apparatus and, more particularly, to a jitter detection apparatus for detecting a jitter component contained in a signal used in a communication system or the like, i.e., a phase variation component.
2. Description of the Related Art
Recently, communication systems as infra-structures for supporting information-oriented societies have assumed greater importance for the next generation. ITU-T (CCITT in the past) has recommended a new synchronous network interface termed a synchronous digital hierarchy (SDH) system as a trunk network for a communication system. Apparatuses to be incorporated in such an SDH system have been developed by PTTs and communication equipment manufacturers in all the countries of the world, and are being put into practice.
In measurement in such an SDH apparatus and system, one of the important factors to be considered is jitter defined as instantaneous fluctuations in the time position of a signal with respect to an ideal time position due to crosstalk or reflection in a digital line.
In order to manage jitter contained in a signal used in an SDH system, ITU-T.sup.2 recommended one of the specifications required for jitter up to a bit rate of STM-16 (2488.32 Mb/s). That is, it specifies that output allowable jitter (Output Jitter, Jitter Generation) must not exceed a specified value in a predetermined jitter frequency band. As a unit of measurement, UI (Unit Interval) is used.
Conventionally, as is known, a jitter detect detection apparatus having a PLL (phase-locked loop) circuit 1 shown in FIG. 10 is used to detect a jitter component contained in a signal used in the above communication system.
The jitter detection apparatus shown in FIG. 10 is equivalent to a PLL structure for jitter measurement, which is disclosed, e.g., "Error Rate.Jitter Measuring Equipment ME520A/B": ANRITSU TECHNICAL 52, pp. 46-50, (especially FIG. 22 of page 46), September 1986.
As shown in FIG. 10, a target signal (to be measured) having a frequency f1, which is input as a jitter detection target, and a signal (reference signal) having a frequency f2 (near the frequency f1) and containing a very small amount of residual jitter component, which is output from a voltage-controlled crystal oscillator (VCXO) 2, are input to a phase/frequency comparator (PFD) 3. The phase/frequency comparator 3 outputs an error signal corresponding to the frequency and phase differences between the two input signals. A component having a frequency higher than the frequency of the signal input to the phase/frequency comparator 3 is removed from the error signal by a jitter detection filter 4. With this operation, a signal containing a jitter component contained in the target signal is extracted as a jitter output. The signal is then input to a low-pass loop filter 5 having a cutoff frequency lower than the frequency of the Jitter component of the target signal. Thereafter, an output signal from the voltage-controlled crystal oscillator 2 is locked to the target signal by a control voltage detected by the loop filter 5.
In the jitter detection apparatus having such a PLL circuit structure, when jitter occurs in a target signal while an output signal from the voltage-controlled crystal oscillator 2 is locked to the target signal, a jitter component contained in the target signal is output from the Jitter detection filter 4, with the output removed from the error signal by a jitter detection filter 4. With this operation, a signal containing a jitter component contained in the target signal is extracted as a jitter output. The signal is then input to a low-pass loop filter 5 having a cutoff frequency lower than the frequency of the Jitter component of the target signal. Thereafter, an output signal from the voltage-controlled crystal oscillator 2 is locked to the target signal by a control voltage detected by the loop filter 5.
In the jitter detection apparatus having such a PLL circuit structure, when jitter occurs in a target signal while an output signal from the voltage-controlled crystal oscillator 2 is locked to the target signal, a jitter component contained in the target signal is output from the Jitter detection filter 4, with the output signal from the voltage-controlled crystal oscillator 2 serving as a reference signal.
Phase variations (jitter) in a target signal can be confirmed by displaying an output from the jitter detection filter 4, indicating it with a meter, or recording it.
The jitter detection apparatus having the above PLL circuit 1 is effective up to a target signal frequency of several 100 MHz. However, accurate detection of jitter in a target signal having a higher frequency (e.g., several GHz) demands a voltage-controlled crystal oscillator and a phase/frequency comparator which exhibit both high stability in such a high frequency band and good linearity. Such an arrangement is difficult to realize in practice. Even if this arrangement can be realized, the overall cost of the apparatus becomes very high.
As a technique for solving this problem, the following technique has been known.
As shown in FIG. 11, in this technique, a target signal is frequency-divided by N using a frequency divider 6, and the resultant signal is input to a PLL circuit 1. An output signal from a voltage-controlled crystal oscillator 2 in the PLL circuit 1 is then locked to this frequency-divided signal.
In the above technique of locking an output signal from the voltage-controlled crystal oscillator to a signal obtained by frequency-dividing a target signal using the frequency divider, the phase modulation degree of the frequency-divided output is smaller than that of the target signal by the degree of frequency division, resulting in a deterioration in jitter detection sensitivity.
For example, if the initial phase of a target signal is ignored, a target signal which is phase-modulated with a sinusoidal wave can be given by EQU Ea=A cos {.omega..sub.1 t+.beta.cos (.omega..sub.m t)}
where .omega..sub.1 is the angular frequency of a carrier wave, .omega..sub.m is the angular frequency of a modulated wave, and .beta. is the modulation degree. In contrast to this, when this target signal is frequency-divided by N, the resultant output signal is given by EQU Eb=B cos {(.omega..sub.1 t/N)+(.beta./N) cos (.omega..sub.m t)}
That is, the frequency of the carrier wave decreases to 1/N, and the modulation degree also decreases to .beta./N. Therefore, when the phase-modulated wave of this signal is detected, the output level is lower than that of the phase-modulated wave of the target signal corresponding to the frequency division ratio.